1. Field of the Invention
The present invention relates to the field of clocking apparatus for computer systems; more specifically, the present invention relates to circuitry for generation of clock signals in a multi-processor computer system.
2. Description of the Related Art
Modern day computer systems operate under the control of one or more "clocks" or signal lines carrying a signal of a predetermined frequency and duty cycle. The clock signal is provided to various components in the computer system and these components typically carry out some operation or set of operations during one or more "clock cycles" or cycles of the signal. A crystal or other device is used to generate the clock signal, such crystals being capable of generating clock signals at predetermined frequencies such as 8 Mhz, 16 Mhz, 32 Mhz and 64 Mhz.
Of course, the various components of the computer system must be designed to match the clock speed or frequency. More properly put, the computer system must be designed to provide a clock signal of the appropriate clock speed to circuits used in the computer system. The circuits are typically purchased or otherwise acquired by the computer system designer having a specified clock speed. It follows that should one of the components be changed or upgraded with a component having a different required clock input frequency that the computer system must be redesigned to provide for an additional clock input.
This creates a special problem in multiple processor computer systems where it is desired to operate all components under the control of a single clock and, for example, only one of the processor modules is upgraded with a higher speed processor. Alternatively, all processors may be upgraded but other components in the system may still require a lower speed clock. One solution to this problem may be to provide a higher speed systems clock (e.g., upgrade the system clock from being a 32 Mhz clock to being a 64 Mhz clock) in order to the satisfy the needs of the processors and then to provide clock division circuitry to divide the clock speed to the frequency required by the other components.
However, in the computer system of the present invention the system clock is provided on a backplane with which numerous circuit boards, such as processor boards, are coupled. Replacement of the backplane, or the clock circuitry on the backplane, to provide a higher speed clock is expensive and, further, would require field service of each installed system to accomplish the desired replacement.
Therefore, what is desired is to develop clock generation circuitry which provides increased clock speed without the requirement of replacing the system clock.
It should be noted that the preferred embodiment of the present invention is designed for implementation on a computer system available from Stardent Computer, Inc. of Newton, Mass. FIG. 4, which will be explained in greater detail below, illustrates certain clock generation circuitry of a prior art computer system available from Stardent Computer, Inc. under the tradename TITAN. The prior art TITAN computer utilizes a microprocessor manufactured by MIPS Computer Systems, Inc. of Sunnyvale, Calif. under the tradename R2000. The R2000 microprocessor requires a 32 Mhz clock signal. In the preferred embodiment of the present invention, processor boards may utilize a microprocessor available from MIPS Computer Systems Inc. under the tradename R3000. The R3000 microprocessor requires a 64 Mhz clock signal.